1. Field of the Invention
This invention relates to the field of the prevention of reverse engineering of integrated circuits and/or making such reverse engineering so difficult and time-consuming as to make reverse engineering of integrated circuits non-feasible.
More particularly, this invention relates to using, in order to prevent and/or discourage such reverse engineering, vias (i.e., holes etched in the oxide layers between metal layers and then filled with metal to affect a connection between metal layers) either not beginning on a metal layer or not terminating on a metal layer.
2. Description of the Related Art
The design and development of semiconductor integrated circuits require a thorough understanding of the complex structures and processes and involve many man-hours of work requiring high skill, costing considerable sums of money.
In order to avoid this time and effort, some developers resort to the practice of reverse engineering, disassembling existing devices manufactured by somebody else, and closely examining them to determine the physical structure of the integrated circuit, followed by slavishly copying the device. Thus, by obtaining a planar optical image of the circuits and by studying and copying them, typically required product development efforts are circumvented.
Such practices hurt the true developer of the product and impairs its competitiveness in the market-place, because the developer had to spend significant amounts of time and effort for the development, while the reverse engineer did not have to.
A number of approaches has been used in order to frustrate such reverse engineering attempts, particularly in the field of semiconductor integrated circuits.
For instance, U.S. Pat. No. 5,866,933 to Baukus, et. al. teaches how transistors in complementary metal oxide-semiconductor (CMOS) circuit can be connected by implanted, hidden and buried lines between the transistors. This hiding is achieved by modifying the p+ and n+ source/drain masks. The implanted interconnections are further used to make a 3-input AND-circuit look substantially the same as a 3-input OR-circuit.
Furthermore, U.S. Pat. No. 5,783,846 to Baukus, et. al. and U.S. Pat. No. 5,930,663 to Baukus et. al. teach a further modification in the source/drain implant masks, so that the implanted connecting lines between transistors have a gap inserted, the length of which is approximately the length of the feature size of the CMOS technology being used. These gaps are called xe2x80x9cchannel blocks.xe2x80x9d
If the gap is xe2x80x9cfilledxe2x80x9d with one kind of implant (depending on whether the implanted connecting line is xe2x80x9cpxe2x80x9d or xe2x80x9cnxe2x80x9d), the line conducts; if another kind of implant is used for the gap-filling, the line does not conduct. The reverse engineer must determine connectivity on the basis of resolving the xe2x80x9cnxe2x80x9d or xe2x80x9cpxe2x80x9d implant at the minimum feature size of the channel block. In addition, transistor sizes and metal connection routings are modified, in order to deprive the reverse engineer of using clues with which he can find inputs, outputs, gate lines and so on as keys to the circuit functionality.
Practicing the inventions taught in the above-mentioned patents to secure an integrated circuit causes the reverse engineer to perform steps that are not always needed. These steps include: decomposing the circuit layer by layer, careful processing of each layer followed by imaging of the layer with exact registration to other layers, and having the required process to image and determine small area implants of specifically both and p-types.
Once a particular standard circuit functionality has been determined, the reverse engineer will attempt to find some signature in the metal layers of that standard circuit which can exactly indicate the presence of that particular standard circuit in other places in the integrated circuit. If this can be done, that information can be entered into the reverse engineer""s data base and automatic pattern recognition of the metal pattern is used to determine the circuit, without need for the extensive delayering. This would save considerable time and effort.
Therefore, there still exists a need for an inexpensive, easy-to-implement defensive method which can help to provide the enhanced protection against the reverse engineering of semiconductor integrated circuits, in particular to make such a signature impossible to determine. The present invention provides such a method.
This invention makes the use of vias to provide connections between metal layers unpredictable and difficult to be determined accurately. Hence, the circuit will appear to be one thing, while in fact it is something else. This is a good way to prevent reverse engineering.
Modern integrated circuits are constructed such that signals are routed between circuit/logic blocks (or sometimes between transistors within a single circuit/logic block) and input/output ports, via metallic lines. For purposes of compaction, more than one metal layer is used, the metal layers being separated by a deposited insulating layer, both metal layers being disposed on top of the semiconductor substrate. Connections between these metal lines are accomplished by using vias, for example, holes etched in the insulating layer between metals. The vias are filled with a metal, typically, tungsten.
The gravamen of the present invention is to provide vias which either do not begin or do not terminate on a metal layer. Such non-metal terminating vias will look like an interconnection between adjacent metal layers/lines to the reverse engineer, but they in fact provide no such interconnection.
Such non-metal terminating vias will make it very difficult for a reverse engineer to determine what the signal routing pattern really is, making the process of reverse engineering more expensive and time consuming effectively rendering the circuit secure from such intrusion.
When the reverse engineer observes the top metal layer, dimples in the metal indicate the presence of vias. He will also observe the presence of the via after having removed the top metal layer. However, as a result of etching away the oxide layer between metal layers, down to the lower metal layer, the via is eliminated as well. Therefore, the reverse engineer is likely to assume that the metal layers are connected, because following the via to the lower level, where in fact it is not connected to the lower metal layer, is difficult to accomplish.
The reverse engineer will have to assume the via connects with two metal lines, one in the upper metal layer and one in the lower metal layer, while in fact, the connection is only with, at most, one metal layer.
A first aspect of the invention provides a semiconducting device adapted to prevent and/or to thwart reverse engineering, including an insulating layer disposed on a semiconductor substrate, a first metal layer and a second metal layer, said first metal layer and second metal layer being separated by said insulating layer and a via defined by said insulating layer, said via having a first end and a second end, wherein said first end of said via is connected to said first metal layer and said second end of said via terminates prior to reaching said second metal layer.
A second aspect of the invention provides a semiconducting device adapted to prevent and/or to thwart reverse engineering, including an insulating layer disposed on top of semiconductor substrate a first metal layer and a second metal layer, said first metal layer and second metal layer being separated by said insulating layer, and a via defined by said insulating layer, said via having a first end and a second end, wherein said second end of said via is connected to said second metal layer and said first end of said via terminates prior to reaching said first metal layer.
A third aspect of the invention provides a method for preventing and/or thwarting reverse engineering, comprising steps of disposing an insulating layer on top of semiconductor substrate, forming and patterning a first metal layer and a second metal layer so that said first metal layer and said second metal layer are separated by said insulating layer and forming a via defined by said insulating layer, said via having a first end and a second end, wherein said first end of said via is connected to said first metal layer and said second end of said via terminates prior to reaching said second metal layer.
A fourth aspect of the invention provides a method for preventing and/or thwarting reverse engineering, comprising steps of disposing an insulating layer on top of semiconductor substrate, forming and patterning a first metal layer and a second metal layer so that said first metal layer and said second metal layer are separated by said insulating layer, and forming a via defined by said insulating layer, said via having a first end and a second end, wherein said second end of said via is connected to said second metal layer and said first end of said via terminates prior to reaching said first metal layer.